1. Field of Invention
This invention relates to integrated circuit packages and, more particularly, to a path of heat transfer in a lateral direction from a periphery of the integrated circuit to a stiffener dimensioned substantially close to the periphery.
2. Description of Related Art
During manufacture of an integrated circuit (e.g., a microprocessor), signal lines formed upon a silicon substrate (i.e., chip) and to be connected to external devices are terminated at flat metal contact regions called input/output (I/O) pads. Following manufacture, the integrated circuit is typically secured within a protective semiconductor device package. Each I/O pad of the chip is then connected to one or more terminals of the device package. The terminals of a device package are typically arranged about the periphery of the package. Fine metal wires are typically used to connect the I/O pads of the chip to the terminals of the device package. Some types of device packages have terminals called "pins" for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called "leads" for attachment to flat metal contact regions on an exposed surface of a PCB. Newer ball grid array ("BGA") packages described below have solder balls for attachment to flat metal pads on an exposed surface of a PCB.
As integrated circuit fabrication technology improves, manufacturers are able to integrate more and more functions onto a single silicon chip. As the number of functions on a single chip increases, the number of signal lines which need to be connected to external devices also increase. The corresponding number of required I/O pads and device package terminals increase as well, as do the complexities and costs of the device packages. Constraints of high-volume PCB assembly operations place lower limits on the physical dimensions of device packages and distances between device package terminals. As a result, the areas of peripheral-terminal device packages having hundreds of terminals are largely proportional to the number of terminals. In addition, the lengths of signal lines from chip I/O pads to device package terminals increase with the number of terminals, and the high-frequency electrical performance of larger peripheral-terminal device packages suffer as a result.
The controlled collapse chip connection ("C4") is a well known method of attaching an integrated circuit chip directly to a substrate (e.g., a PCB), and is commonly referred to as the "flip chip" method. In preparation for C4 attachment, the I/O pads of the chip are arranged in a two-dimensional array upon an underside of the chip, and a corresponding set of bonding pads are formed upon an upper surface of the substrate. A solder ball is formed upon each of the I/O pads of the chip. During C4 attachment of the chip to the substrate, the solder balls are placed in physical contact with the bonding pads of the substrate. The solder balls are then heated long enough for the solder to reflow. When the solder cools, the I/O pads of the chip are electrically and mechanically coupled to the bonding pads of the substrate. After the chip is attached to the substrate, the region between the chip and the substrate is filled with an "underfill" material which encapsulates the C4 connections and provides other mechanical advantages.
Like flip chips, grid array semiconductor device packages have terminals arranged in a two-dimensional array across the underside surface of the device package. As a result, the physical dimensions of grid array device packages having hundreds of terminals are much smaller than their peripheral-terminal counterparts. Such smaller packages are highly desirable in portable device applications such as laptop and palmtop computers and hand-held communications devices such as cellular telephones. In addition, the lengths of signal lines from chip I/O pads to device package terminals are shorter, thus the high-frequency electrical performances of grid array device packages are typically better than those of corresponding peripheral-terminal device packages. Grid array device packages also allow the continued use of existing PCB assembly equipment developed for peripheral-terminal devices.
An increasingly popular type of grid array device package is the BGA device package. A BGA device includes a chip mounted upon a larger substrate made of, for example, fiberglass-epoxy printed circuit board material or ceramic material (e.g., aluminum oxide, alumina, Al.sub.2 O.sub.3, or aluminum nitride, AIN). The substrate includes two sets of bonding pads: a first set adjacent to the chip and a second set arranged in a two-dimensional array across the underside surface of the device package. Members of the second set of bonding pads function as device package terminals. The solder balls on the underside of the BGA device package allow the device to be surface mounted to an ordinary PCB. The I/O pads of the chip are typically connected to corresponding members of the first set of bonding pads by signal lines. The substrate includes one or more layers of signal lines (i.e., interconnects) which connect respective members of the first and second sets of bonding pads. During PCB assembly, the BGA device package is attached to the PCB by reflow of the solder balls just as a flip chip is attached to a substrate.
Semiconductor devices (e.g., integrated circuit chips) dissipate electrical power during operation, transforming electrical energy into heat energy. At the same time, several key operating parameters of a semiconductor device typically vary with temperature, and reliable device operation within specifications occurs only within a defined operating temperature range. For high performance devices, such as microprocessors, specified performance is only achieved when the temperature of the device is below a specified maximum operating temperature. Operation of the device at a temperature above an upper limit of the operating temperature range, or above the maximum operating temperature, may result in irreversible damage to the device. In addition, it has been established that the reliability of a semiconductor device decreases with increasing operating temperature. The heat energy produced by a semiconductor device during operation must thus be removed to the ambient environment at a rate which ensures reliable operation.
The operating temperature of an integrated circuit chip enclosed within a semiconductor device package is governed by: (i) the temperature of the ambient surrounding the device package, (ii) the amount of electrical power dissipated by the chip, and (iii) the sum of thermal resistances of elements and interfaces along a heat transfer path from the chip to the ambient. More complex heat transfer (i.e., cooling) mechanisms, such as heat sinks and forced air cooling, permit semiconductor devices to dissipate more electrical power than direct exposure to the ambient would otherwise allow.
It would be beneficial to have a packaged integrated circuit device including an integrated circuit chip enclosed within a semiconductor device package, wherein the device package includes grid array terminals, and wherein the chip is mounted upon a substrate of the device package using the C4 or flip chip attachment method. The use of C4 attachment would reduce many of the problems associated with using fine metal wires to connect the I/O pads of the chip to corresponding bonding pads of the BGA package, including wire crossover problems and the added electrical inductances of the wires. It would be further desirable to reduce the dimension between the integrated circuit periphery and a cavity inner surface facing the periphery. The cavity inner surface would desirably be formed with a stiffener having a surface which faces the integrated circuit substantially close to the integrated circuit lateral surface to allow heat transfer from the integrated circuit to the stiffener. The addition of a heat transfer path to the stiffener will beneficially improve the overall heat transfer characteristics of the package. Not only will the heat be transferred from the integrated circuit upper and lower surfaces, but the improved configuration also allows heat transfer from the integrated circuit lateral edges. As such, the improved package is best suited for integrated circuits which generate substantial amounts of heat and/or energy.